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for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 1 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz functional diagram features 3.3 v only, single supply rail operation output frequency range: 25 mhz - 2500 mhz integer or fractional-n mode frequency translation conigurable lvds-compatible or lvpecl type differential outputs power priority andperformance priority modes 97 fs rms jitter generation (12 khz - 20 mhz, 2500 mhz, typ) -163 dbc/hz phase noise floor to improve adc/dac snr (maximum output swing levels). adjustable pll loop bw via external filter output disable/mute control lock detect signal exact frequency mode to achieve reference frequency tuning, and 0 hz frequency error 40 lead 6x6 mm smt package: 36 mm 2 typical applications ? 10g/40g/100g optical modules, transponders, line cards ? otn and sonet/sdh applications ? data converters, sample clock generation ? cellular/4g infrastructure ? high frequency processor/fpga clocks ? any frequency clock rate generation ? low jitter saw oscillator replacement ? dds replacement ? frequency translation ? frequency margining information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 2 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz general description the HMC1035LP6GE is a low-noise, wide-band 3.3 v clock generator ic with a frac tional-n phase locked loop (pll) that features an integrated voltage controlled oscillator (vc o). the device provides differential clock outputs between 25 mhz and 2500 mhz range. the HMC1035LP6GE features a low n oise phase detector (pd) and delta-sigma modulator, capable of operating at up to 100 mhz which permits wi der loop-bandwidths and excellent spurious performance. the HMC1035LP6GE features industry leading phase noise and jitter per formance, across the operating range, that enable it to improve link level jitter performance, bit-error-rat es (ber) and eye diagram metrics. the superior noise loor (<-162 dbc/hz) makes the HMC1035LP6GE an ideal source for a vari ety of applications Csuch as clock references for high speed data converters, physical layer devices (phy ), serializer/deserializer (serdes) circuits, fpgas and processors. the HMC1035LP6GE can also be used as an lo for 10g/40 g/100g optical modules and transponders, as well as primary reference clock for 10g/40g/100g l ine cards, and for jitter attenuation and frequency translation. the differential output of the HMC1035LP6GE can be set to either external termination, which could be used for lvpecl operation, or internal termination for operation in a n lvds compatible mode or lvpecl, see figure 18 . additionally, an ouput swing adjustment makes the device lexible and com patible with a wide variety of signal level requirements. the output can be internally terminated to reduce compon ent count and cost or could be terminated externally using standard lvpecl termination methods such as figure 21 . an output mute function allows the user to shut off the outputs, such as may be required for board testing or debugging. the lvpecl/lvds, amplitude select and output mute function are all programmed spi serial programmin g the HMC1035LP6GE is designed to select between a power priority or a perform ance priority mode. the power priority setting reduces the current consumption of the part, whereas t he performance priority setting improves the jitter and phase noise performance. the 24 bit delta-sigma modulator further enhances hittites exact fre quency mode, which enables users to generate output frequencies with 0 hz frequency error in many application s. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 3 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz electrical speciications, vppcp, vddls, 3vrvdd, vcc1, vcc2, vcchf, vccps, vccpd, = 3.3v min & max speciied across temperature -40 c to 85 c parameter condition min. typ. max. units out_n, out_p output characteristics output frequency 25 2500 mhz differential output amplitude gain setting = 0000 690 mvpp gain setting = 0001 780 mvpp gain setting = 0010 900 mvpp gain setting = 0011 980 mvpp gain setting = 0100 110 0 mvpp gain setting = 0101 1260 mvpp gain setting = 0110 1400 mvpp gain setting = 0111 1590 mvpp gain setting = 1000 1810 mvpp gain setting = 1001 1980 mvpp gain setting = 1010 2250 mvpp gain setting = 1011 2560 mvpp output common mode voltage lvds mode 1.2 mv lvpecl mode 2.0 v output rise and fall time lvds mode, gain = 0001 120 ps output rise and fall time lvpecl mode, gain = 0110 130 ps duty cycle ac coupled, measured at the 0 v crossing , 622.080 mhz and 2.5 ghz outputs 49 50 51 % vco output divider vco rf divider range 1,2,4,6,8,...,62 1 62 pll rf divider characteristics 19-bit n-divider range (integer) max = 2 19 - 1 16 524,287 19-bit n-divider range (fractional) fractional nominal divide ratio varies (-3 / +4) dynamically max 20 524,283 clkin input characteristics max input frequency 2 350 mhz input amplitude ac coupled [1] 0.2 3.3 vp-p input capacita nce 5 pf input slew rate 157 mv/ns 14 bit r-divider range 16,383 phase detector (pd) [2] pd frequency fractional mode 0.006 100 mhz pd frequency integer mode 0.006 100 mhz charge pump output current 0.02 2.54 ma charge pump gain step size 20 a pd/charge pump ssb phase noise 50 mhz ref, input referred 1 khz -143 dbc/hz 10 khz add 1 db for fractional -150 dbc/hz 100 khz add 3 db for fractional -152 dbc/hz logic inputs vsw switching threshold for logic levels 40 50 60 % dvdd logic outputs voh output high voltage dvdd v vol output low voltage 0 v output impedance 100 200 maximum load current 1.5 ma information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 4 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz parameter condition min. typ. max. units power supply voltages + 3.3v supplies avdd, vppcp, vddls,3vrvdd, dvdd3v, vcc1, vcc2, vcchf, vccps, vccpd 3.15 3.3 3.5 v power supply currents +3.3v lvpecl, performance priority mode, 2.5 ghz output, excluding load 186 ma lvpecl performance prior- ity mode, 2.5 ghz output, includes termination 218 ma lvpecl performance priority mode, 622.080 mhz output, includes termination 237 ma lvds, power priority mode, 2.5 ghz output, includes termination 173 ma lvds, power priority mode, 622.080 mhz output, includes termination 221 ma power down - crystal off reg 01h=0, crystal not clocked 10 a power down - crystal on, 100 mhz reg 01h=0, crystal clocked 100 mhz 5 ma power on reset typical reset voltage on dvdd 700 mv minimum dvdd voltage for no reset 1.5 v power on reset delay 250 s figure of merit floor integer mode normalized to 1 hz -227 dbc/hz floor fractional mode normalized to 1 hz -226 dbc/hz flicker (both modes) normalized to 1 hz -268 dbc/hz phase jitter rms, integer mode 622.08 mhz output , 12 khz to 20 mhz 107 fs 2.5 ghz output 12 khz -20mhz 97 fs phase jitter rms, fractional mode 622.08 mhz output , 12 khz to 20 mhz 125 fs 2.5 ghz output 12 khz -20mhz 1 10 fs [1] measurements made are ac coupled into a 100 differential load (excep t phase noise). [2] the maximum phase detector frequency can only be achieved if the minumum n value is respected, eg in the case of fractional feedback mode, the maximum pfd rate = fvco/20 or 100 mhz whichever is less. operation > 70m hz may require offsett currents to be disabled and reenabled. electrical speciications (continued) information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 5 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz [1] the pn plot is measured with a 100mhz ocxo followed with a divide by 2, using the loop filter in the loop filter coniguration table [2] the pn plot is measured with 50 mhz crystal oscillator (red) versus a 50mhz ocxo (blue). [3] jitter is integrated over a 12khz to 20mhz band -180 -170 -160 -150 -140 -130 -120 -110 -100 1 10 100 1000 10000 100000 625 mhz_lvds 625 mhz_lvpecl 2500 mhz_lvds 2500 mhz_lvpecl offset(khz) phase noise(hz) -180 -170 -160 -150 -140 -130 -120 -110 -100 1 10 100 1000 10000 100000 625 mhz_lvds 625 mhz_lvpecl 2500 mhz_lvds 2500 mhz_lvpecl offset(khz) phase noise(hz) -180 -170 -160 -150 -140 -130 -120 -110 -100 1 10 100 1000 10000 100000 622.08 mhz_lvds 622.08 mhz_lvpecl 2500 mhz_lvds 2500 mhz_lvpecl offset(khz) phase nose(hz) -180 -170 -160 -150 -140 -130 -120 -110 -100 1 10 100 1000 10000 100000 622.08 mhz_lvds 622.08 mhz_lvpecl 2500 mhz_lvds 2500 mhz_lvpecl offset(khz) phase nose(hz) 40 60 80 100 120 140 160 lvds_pwr_pri lvds_perf_pri lvpecl_pwr_pri lvpecl_pwr_pri integrated rms jitter (fs) 625 frequency (mhz) 2500 -180 -160 -140 -120 -100 -80 1 10 100 1000 10000 100000 xo ocxo offset(khz) phase noise(dbc/hz) figure 1. typical phase noise, integer mode, power priority [1] figure 2. typical phase noise, integer mode, performance priority [1] figure 3. typical phase noise, fractional mode, power priority [1] figure 4. typical phase noise, fractional mode, performance priority [1] figure 5. integer phase noise vs reference source [2] figure 6. jitter from integrated phase noise vs output frequency, integer mode [2] information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 6 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz -200 -150 -100 -50 0 50 100 150 200 -50 0 50 100 150 200 250 300 time( (us) phase error (degree) 200 400 600 800 1000 1200 1400 100 1000 lvds_pwr_pri lvds_perf_pri lvpecl_pwr_pri lvpecl_perf_pri frquency (mhz) vppd (mv) 3000 [4] the HMC1035LP6GE has a preloaded register ile for a 2ghz output and time is m easured from vco disable to vco enable, using the loop filter in the loop filter coniguration table. [5] the output signal amplitude is measured with hmc1035 ac coupled to a 100 o hm differntial loadinstrument [6] measured at 20% to 80% levels. 40 60 80 100 120 140 160 lvds_pwr_pri lvds_perf_pri lvpecl_pwr_pri lvpecl_pwr_pri integrated rms jitter (fs) 2500 622.08 frequency (mhz) -50 0 50 100 150 200 250 300 time( (us) frequency error (hz) 2 10 9 60 80 100 120 140 160 lvds_pwr_pri lvds_perf_pri lvpecl_pwr_pri lvpecl_perf_pri rise time (ps) 2500 622.08 frequency (m) 60 80 100 120 140 160 lvds_pwr_pri lvds_perf_pri lvpecl_pwr_pri lvpecl_perf_pri f all time (ps) 2500 622.08 frequenc (m) figure 7. jitter from integrated phase noise vs. frequency, fractional mode [3] figure 8. lock time vs. phase error [4] figure 9. lock time vs frequency error [4] figure 10. output amplitude vs output frequency [5] figure 11. output rise time vs. output frequency [6] figure 12. output fall time vs. output frequency information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 7 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz loop filter bw (khz) c1 (pf) c2 (nf) c3 (pf) c4 (pf) r2 () r3 () r4 () loop filter design 127 390 10 82 82 750 300 300 75 270 27 200 390 430 390 390 loop filter coniguration table 100 120 140 160 180 200 220 lvdsl owi lvdsl own l vpec ll owi l vpec ll own idd(ma) fo/16 fo/4 fo/8 fo fo/2 frequency [7] duty cycle is measured with the output ac coupled at the 0 crossing level. [8] the current is measured at nominal vco vdd supply under fractional loc ked condition by varying different the output divider ratio. 47 48 49 50 51 52 lvds_pwr_pri lvds_perf_pri lvpecl_pwr_pri lvpecl_perf_pri duty cycle (%) 2500 622.08 frequency () -1500 -1000 -500 0 500 1000 1500 00 . 511 . 522 . 53 lvds perf pri lvds pwr pri lvpecl perf pri lvpecl pwr pri time (ns) vppd (mv) figure 13. output duty cycle vs. output frequency [7] figure 14. supply current vs. output frequency [8] figure 15. output amplitude vs. gain setting over temperature figure 16. out waveform, performance priority and power priority in lvds and lvpecl mode 500 1000 1500 2000 2500 3000 024681 0 vppd (mv) 27c -40c 85c gain setting step information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 8 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz outline drawing notes: 1. package body material: low stress injection molded plastic silica and silicon impregnated. 2. lead and ground paddle material: copper alloy. 3. lead and ground paddle plating: 100% matte tin. 4. dimensions are in inches [millimeters]. 5. lead spacing tolerance is non-cumulative. 6. pad burr length shall be 0.15mm max. pad burr height shall be 0.25mm max. 7. package warp shall not exceed 0.05mm. 8. all ground leads and ground paddle must be soldered to pcb rf ground. 9. refer to hittite application note for suggested pcb land pattern. absolute maximum ratings avdd, vppcp, vddls, 3vrvdd, dvdd3v, vcc1, vcc2, vcchf, vccps, vccpd -0.3v to +3.6v operating temperature -40 c to +85c storage temperature -65 c to 150c maximum junction temperature 125 c thermal resistance (r th ) (junction to ground paddle) 10 c/w relow soldering peak temperature 260c time at peak temperature 40 sec esd sensitivity (hbm) class 1b stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this speciication is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. part number package body material lead finish msl rating package marking [1] HMC1035LP6GE rohs-compliant low stress injection molded plastic 100% matte sn msl1 h1035 xxxx [1] 4-digit lot number xxxx package information information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 9 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz pin descriptions pin number function description 1 avdd 3.3 vdc power supply for analog circuitry 2, 5, 6, 8, 9, 11 - 14, 18 - 22, 24, 26, 34, 37, 38 nc the pins are not connected internally; however, all data shown herein was measured with these pins connected to rf/dc ground externally. 3 vppcp 3.3v power supply for charge pump analog section 4 cp charge pump output 7 vddls 3.3v power supply for the charge pump digital section 10 3vrvdd reference supply 15 xrefp reference oscillator input 16 dvdd3v 3.3v dc power supply for digital (cmos) circuitry 17 cen chip enable. connect to logic high for normal operation. 23 vtune vco varactor. tuning port input. 25 vcc2 3.3v vco analog supply 2 27 vcc1 3.3v vco analog supply 1 28 out_n negative output signal (differential) 29 out_p positive output signal (differential) 30 sen pll serial port enable (cmos) logic input 31 sdi pll serial port data (cmos) logic input 32 sck pll serial port clock (cmos) logic input 33 ld/sdo lock detect, or serial data, or general purpose (cmos) logic output (gp o) 35 vcchf 3.3 v dc power supply for analog circuitry 36 vccps 3.3 v dc power supply for analog prescaler 39 vccpd 3.3 v dc power supply for phase detector 40 bias external bypass decoupling for precision bias circuits. note: 1.920v 20mv reference voltage (bias) is generated internally a nd cannot drive an external load. must be measured with 10g meter such as agilent 34410 a, normal 10m dvm will read erroneously. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 10 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz evaluation pcb schematic the circuit board used in the application should use rf circuit design tec hniques. signal lines should have 50 ohm impedance while the package ground leads and exposed paddle should be con nected directly to the ground plane similar to that shown. a sufficient number of via holes should be use d to connect the top and bottom ground planes. the evaluation circuit board shown is available from hittite upon reques t. the hmc1035 evaluation board and associated software offers the user an e asy way to quickly evaluate the performance and lexibility of the hmc1035. the evaluation board oper ates off a +5v supply and includes an hmc1060 ldo, which generates a low noise 3.3v source, and a precision pll which gene rates a 50mhz clock, which is locked to an externally supplied 10 mhz reference. the pll design is an hmc1031 phase/frequency detector, passive loop ilte r and a low noise 50 mhz vcxo. the pll is normally, or default upon shipping, set to lock on to a 10 mhz reference feed into r ef in. a 5mhz input reference can be used if d1, d0 is reconigured to 1,1, or 50 mhz if d1, d0 is reconigured to 0,1. the ref in would normally have a +/-50 ppm tolerance which falls within the vcxo pull range. a lthough not recommended, the hmc1035 eb can be operated without supplying an external reference, and the pll will p ull the vcxo to about 49.992 mhz, or 180 ppm low. alternatively, an external 50 mhz reference can be feed into the hm c1035 evaluation board which requires removing c44,c35, r32 and j6, the tpll/tcxo, and placing a 0 ohm r esistor in the r20 and r36 locations. to view this evaluation pcb schematic please visit www.hittite.com and choose HMC1035LP6GE from the ?search by part number? pull down menu to view the product splash page. evaluation pcb item contents part number evaluation pcb only HMC1035LP6GE evaluation pcb eval01-HMC1035LP6GE evaluation kit HMC1035LP6GE evaluation pcb usb interface board 6 usb a male to usb b female cable cd rom (contains user manual, evaluation pcb schematic, evaluati on software, hittite pll design software) ekit01-HMC1035LP6GE evaluation order information eval01-hmc1035lp6g ekit01-hmc1035lp6g hmc1035lp6g evaluation pcb hmc1035lp6g evaluation pcb information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 11 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz HMC1035LP6GE input stage a representative schematic for the HMC1035LP6GE output stage is given i n figure 17 below. the buffer is internally dc biased with 100 ohm internal termination. for 50 ohm match, an exte rnal 100 ohm resistor to ground should be added, followed by an ac coupling capacitor (impedance < 1 ohm) then to the xrefp p in of the part. HMC1035LP6GE output stage a representative schematic for the HMC1035LP6GE output stage is given i n figure 18 below. the output is derived from an emitter which can be internally biased to a current source (the default s etting), or the internal termination switch can be opened, vco_reg03[4], and external termination used. th e internal bias would be used when lvds levels are required and the load would normally be a 100 differential load as sh own in figure 19. with the internal bias set, the HMC1035LP6GE output can also be used to drive 50 ohm si ngle ended loads, see figures 19 and 20. this would simplify lvpecl designs and reduce component cost. figure 17. input stage figure 18. output stage figure 19. ac coupling into 100 ohm differential load figure 20. ac coupling into a 50 ohm load information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 12 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz alternatively, the user can disable the internal bias, vco_reg 03h [4]=0, and use a standard lvpecl termination scheme. one of the most common methods is shown in figure 21, with the resistors b eing located near the receiver. ac coupling can be used after the dc biasing resistor network the outputs can either be dc or ac coupled and the loads may be internal to the recei ver or adc etc - consult the manufacture for internal biasing and loading requirements. selec ting the ac coupling capacitors is a balance between impedance loading and rise and fall time versus signal loss and dc level droo ping during the logic high and logic low levels - a low value such as 10 pf can be used for high frequency signals in the ghz range to e nsure optimized rise and fall times, while a 100 nf capacitor can be used to insure low loss and minimal dc dr ooping when the output is a low value such as 25 mhz. waveform diagrams see figure 22 which shows the deinition for rise and fall time as wel l as vcm and vamp. figure 23 shows the duty cycle, which is deined as (on time/period) were on time is positive going/ logic high level . measurements are made using the internal bias setting. figure 22. rise and fall time, v cm v amp figure 23. duty cycle figure 21. lvpecl termination information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 13 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz 1.1 serial port 1.1.1 serial port modes of operation the HMC1035LP6GE serial port interface can operate in two different mode s of operation. a. hmcspi hmc mode (hmc legacy mode) - single slave per hmcspi bus b. hmcspi open mode - up to 8 slaves per hmcspi bus. both modes support 5-bits of register address space. hmc mode can support u p to 6 bits of register address. register 0 has a dedicated function in each mode. open mode allows wider com patibility with other manufacturers spi protocols. register 0 comparison - single vs multi-user modes single user hmc mode multi-user open mode read chip id 24-bits chip id 24-bits write soft reset, general strobes read address [4:0] soft reset [5] general strobes [23:6] 1.1.2 hmcspi protocol decision after power-on reset on power up both types of modes are active and listening. a decision to select the desired spi protocol is made on the irst occurrence o f sen or sclk following a hard reset, after which the protocol is ixed and only changeable by cycling the p ower off and on. a. if a rising edge on sen is detected irst hmc mode is selected. b. if a rising edge on sclk is detected irst open mode is selected. 1.1.3 serial port hmc mode - single pll hmc mode (legacy mode) serial port operation can only address and talk to a sing le pll, and is compatible with most hittite plls and plls with integrated vcos. the hmc mode protocol, shown in figure 24 and, figure 25 is designed for a 4 wire interface with a ixed protocol featuring a. 1 read/write bit b. 6 address bits c. 24 data bits d. 3 wire for write only, 4 wire for read/write capability information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 14 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz 1.1.3.1 hmc mode - serial port write operation avdd = dvdd = 3.3v 5%, agnd = dgnd = 0v spi hmc mode - write timing characteristics parameter conditions min. typ. max units t 1 sen to sclk setup time 8 ns t 2 sdi to sclk setup time 3 ns t 3 sclk to sdi hold time 3 ns t 4 sen low duration 20 ns t 5 sck to sen fall 10 ns max serial port clock speed 50 mhz a typical hmc mode write cycle is shown in figre 24. a. the master (host) both asserts sen (serial port enable) and clears sdi to indicate a write cycle, followed by a rising edge of sck. b. the slave (synthesizer) reads sdi on the 1st rising edge of sck after sen . sdi low indi cates a write cycle (/wr). c. host places the six address bits on the next six falling edges of sck, msb irs t. d. slave shifts the address bits in the next six rising edges of sck (2-7). e. host places the 24 data bits on the next 24 falling edges of sck, msb irst. f. slave shifts the data bits on the next 24 rising edges of sck (8-31). g. the data is registered into the chip on the 32nd rising edge of sck. h. sen is cleared after a minimum delay of t 5 . this completes the write cycle. figure 24. hmc mode - serial port timing diagram write 1.1.3.2 hmc mode - serial port read operation a typical hmc mode read cycle is shown in figure 25. a. the master (host) asserts both sen (serial port enable) and sdi to indic ate a read cycle, followed by a rising edge sclk. note: the lock detect (ld) function is usually multi plexed onto the ld_sdo pin. it is suggested that ld only be considered valid when sen is low. in fact ld w ill not toggle until the irst active data bit toggles on ld_sdo, and will be restored immediately af ter the trailing edge of the lsb of serial data out as shown in figure 25. b. the slave (HMC1035LP6GE) reads sdi on the 1st rising edge of sclk after sen . sdi high initiates the read cycle (rd) information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 15 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz c. host places the six address bits on the next six falling edges of sclk, msb irs t. d. slave registers the address bits on the next six rising edges of sclk (2-7). e. slave switches from lock detect and places the requested 24 data bi ts on sd_ldo on the next 24 rising edges of sck (8-31), msb irst . f. host registers the data bits on the next 24 falling edges of sck (8-31). g. slave restores lock detect on the 32nd rising edge of sck. h. de-assertion of sen completes the cycle spi hmc mode - read timing characteristics parameter conditions min. typ. max units t 1 sen to sclk setup time 8 ns t 2 sdi to sclk setup time 3 ns t 3 sclk to sdi hold time 3 ns t 4 sen low duration 20 ns t 5 sclk to sdo delay 8.2ns+0.2ns/pf ns t 6 recovery time 10 ns figure 25. hmc mode - serial port timing diagram - read 1.1.4 serial port open mode the serial port open mode, shown in figure 26 and figure 27 , features: a. compatibility with general serial port protocols that use shift and str obe approach to communication b. compatible with hittite pll with integrated vco solutions, useful to ad dress multiple chips of various types from a single serial port bus. the open mode protocol has the following general features: a. 3-bit chip address , can address up to 8 devices connected to the serial bus b. wide compatibility with multiple protocols from multiple vendors c. simultaneous write/read during the spi cycle information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 16 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz d. 5-bit address space e. 3 wire for write only capability, 4 wire for read/write capability hittite plls with integrated vcos support open mode. some legacy pll and m icrowave plls with integrated vcos only support hmc mode. consult the relevant data sheets f or details. typical serial port operation can be run with sclk at speeds up to 50 mhz. 1.1.4.1 open mode - serial port write operation avdd = dvdd = 3.v 5%, agnd = dgnd = 0v spi open mode - write timing characteristics parameter conditions min. typ. max units t 1 sdi setup time to sclk rising edge 3 ns t 2 sclk rising edge to sdi hold time 3 ns t 3 sen low duration 10 ns t 4 sen high duration 10 ns t 5 sclk 32 rising edge to sen rising edge 10 ns t 6 recovery time 20 ns max serial port clock speed 50 mhz a typical write cycle is shown in figure 26. a. the master (host) places 24-bit data, d23:d0, msb irst, on sdi on the irs t 24 falling edges of sclk. b. the slave (HMC1035LP6GE) shifts in data on sdi on the irst 24 rising edges o f sclk c. master places 5-bit register address to be written to, r4:r0, msb i rst, on the next 5 falling edges of sclk (25-29) d. slave shifts the register bits on the next 5 rising edges of sclk (25-29). e. master places 3-bit chip address, a2:a0, msb irst, on the n ext 3 falling edges of sclk (30-32). hittite reserves chip address a2:a0 = 000 for all rf pll with integrated vcos. f. slave shifts the chip address bits on the next 3 rising edges of sclk (30-32 ). g. master asserts sen after the 32nd rising edge of sclk. h. slave registers the sdi data on the rising edge of sen. figure 26. open mode - serial port timing diagram - write information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 17 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz 1.1.4.2 open mode - serial port read operation a typical read cycle is shown in figure 27. in general, in open mode the ld_sdo line is always active during the write cycle. during any open mode spi cycle ld_sdo will contain the data from the current address writte n in reg 00h [4:0]. if reg 00h [4:0] is not changed then the same data will always be present on ld_sdo when an o pen mode cycle is in progress. if it is desired to read from a speciic address, it is necessar y in the irst spi cycle to write the desired address to reg 00h [4:0], then in the next spi cycle the desired data will be available on ld_sdo. an example of the open mode two cycle procedure to read from any random address is as f ollows: a. the master (host), on the irst 24 falling edges of sclk places 24-bit dat a, d23:d0, msb irst, on sdi as shown in figure 27. d23:d5 should be set to zero. d4:d0 = address of the register to b e read on the next cycle. b. the slave (HMC1035LP6GE) shifts in data on sdi on the irst 24 rising edges o f sclk c. master places 5-bit register address , r4:r0, (the read address re gister), msb irst, on the next 5 falling edges of sclk (25-29). r4:r0=00000. d. slave shifts the register bits on the next 5 rising edges of sclk (25-29). e. master places 3-bit chip address, a2:a0, msb irst, on the next 3 falling e dges of sclk (30-32)..chip address is always 000 for rf pll with integrated vcos. f. slave shifts the chip address bits on the next 3 rising edges of sclk (30-32 ). g. master asserts sen after the 32nd rising edge of sclk. h. slave registers the sdi data on the rising edge of sen. i. master clears sen to complete the address transfer of the two part read cy cle. j. if one does not wish to write data to the chip at the same time as we do the second cycle , th en it is recommended to simply rewrite the same contents on sdi to register zero on th e read back part of the cycle. k. master places the same sdi data as the previous cycle on the next 32 falling e dges of sclk. l. slave (HMC1035LP6GE) shifts the sdi data on the next 32 rising edges of s clk. m. slave places the desired read data (ie. data from the address speciied in reg 00h [7:3] of the irst cycle) on ld_sdo which automatically switches to sdo mode from ld mode, disa bling the ld output. n. master asserts sen after the 32nd rising edge of sck to complete the cycle an d revert back to lock detect on ld_sdo. spi open mode - read timing characteristics parameter conditions min. typ. max units t 1 sdi setup time to sclk rising edge 3 ns t 2 sclk rising edge to sdi hold time 3 ns t 3 sen low duration 10 ns t 4 sen high duration 10 ns t 5 sclk rising edge to sdo time 8.2ns+0.2ns/pf ns t 6 recovery time 10 ns t 7 sck 32 rising edge to sen rising edge 10 ns information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 18 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz 1.1.4.3 hmcspi open mode read operation - 2 cycles figure 27. serial port timing diagram - read for more information on using the gpo pin while in spi open mode please see sect ion 1.15 . information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 19 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz 1.2 coniguration at start-up to conigure the pll after power up, follow the instructions below: 1. conigure the reference divider (write to reg 02h ), if required. 2. conigure the delta-sigma modulator (write to reg 06h ). ? coniguration involves selecting the mode of the delta-sigma modulato r (mode a or mode b), selection of the delta-sigma modulator seed value, and conig uration of the delta-sigma modulator clock scheme. it is recommended to use the values found in the hittite pll evalu ation board control software register iles. 3. conigure the charge pump current and charge pump offset current (writ e to reg 09h ) 4. conigure the vco subsystem (write to reg 05h , for more information see section 1.3.1 , and vco subsystem register map . detailed writes to the vco subsystem via pll reg 05h at start-up are available in the register setting files found in the hittite p ll evaluation software received with a product evaluation kit or downloaded from www.hittite.com . 5. program the frequency of operation ? program the integer part (write to reg 03h ) ? program the fractional part (write to reg 04h ) 6. conigure the vco output divider, if needed in the vco subsystem via pll reg 05h . once the HMC1035LP6GE is conigured after startup, in most cases the user onl y needs to change frequencies by writing to reg 03h integer register, reg 04h fractional register, and reg 05h to change the vco output divider or doubler setting if needed, and possibly adjust the ch arge pump settings by writing to reg 09h for detailed and most up-to-date start-up coniguration please refe r to the appropriate register setting files found in the hittite pll evaluation software received with a pro duct evaluation kit or downloaded from www.hittite.com . 1.3 vco serial port interface (spi) the HMC1035LP6GE communicates with the internal vco subsystem via an int ernal 16 bit vco serial port, (e.g. see figure 25 ). the internal serial port is used to control the step tuned vco and other vco subsystem functions, such as rf output divider / doubler control and rf buf fer enable. note that the internal vco subsystem spi (vspi) runs at the rate of the autocal f sm clock, t fsm , where the fsm clock frequency cannot be greater than 50 mhz. the vspi clock rat e is set by reg 0ah [14:13] with a default setting = 1, or xrefp divided by 4 . writes to the vcos control registers are handled indirectly, via writes to reg 05h of the pll. a write to pll reg 05h causes the pll subsystem to forward the packet, msb irst, across its internal s erial link to the vco subsystem, where it is interpreted. the vco serial port has the capability to communicate with multiple subsyst ems inside the ic. for this reason each subsystem has a subsystem id, reg 05h [2:0]. each subsystem has multiple registers to control the function s internal to the subsystem, which may be different from one subsystem to the next. hence each subsystem has internal reg ister addresses bits ( reg 05h 6:3]) finally the data required to conigure each register within the vco subsyste m is contained in reg 05h [15:7]. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 20 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz 1.3.1 vspi use of reg05h the packet data written into, reg 05h is sub-parsed by logic at the vco subsystem into the following 3 ields: 1. [2:0] - 3 bits - vco_id, target subsystem address = 000b. 2. [6:3] - 4 bits - vco_regaddr, the internal register address inside the vc o subsystem. 3. [15:7] - 9- bits- vco_data, data ield to write into the vco register. for example, to write 0_0011_1110 into register 2 of the vco subsystem (vco_id = 000b), and set the vco output divider to divide by 62, the following needs to be written to reg 05h =0_0011_1110, 0010, 000 b. during autocal, the autocal controller only updates the data ield of reg 05h . the vco subsystem register address ( reg 05h [6:3]) must be set to 0000 for the autocal data to be sent to the correct address. vco subsystem id and register address are not modiied by the autocal state mach ine. hence, if a manual access is done to a vco subsystem register the user must reset the registe r address to zero before a change of frequency which will re-run autocal. since every write to reg 05h will result in a transfer of data to the vco subsystem, if the vco subsystem needs to be reset manually, it is important to make sure that the vco switch settings are not changed. hence the switch settings in reg 10h [7:0] need to be read irst, and then rewritten to reg 05h [15:8]. in summary, irst read reg 10h , then write to reg 05h as follows: reg 10h [7:0] = vv x yyyyy reg 05h = vv x yyyyy 0 0000 iii reg 05h [2:0] = iii, subsystem id, 3 bits (000) reg 05h [6:3] = 0000, subsystem register address reg 05h [7] = 0 , calibration tune voltage off reg 05h [12:8] = yyyyy, vco caps reg 05h [13] = x, dont care reg 05h [15:14] = vv, vco select 1.0 pll register map 1.1 reg 00h id register (read only) bit type name width default description [23:0] ro chip_id 24 a7975 HMC1035LP6GE chip id 1.2 reg 00h open mode read address/rst strobe register (write only) bit type name width default description [4:0] wo read address 5 - (write only) read address for next cycle - open mode only [5] wo soft reset 1 - soft reset - both spi modes reset (set to 0 for proper operation) [23:6] wo not deined 18 - not deined (set to 0 for proper operation) information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 21 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz 1.3 reg 01h rst register (default 000002h) bit type name width default description [0] r/w reserved 1 0 reserved [1] r/w reserved 1 1 reserved [2] r/w reserved 1 0 reserved [3] r/w reserved 1 0 reserved [4] r/w reserved 1 0 reserved [5] r/w reserved 1 0 reserved [6] r/w reserved 1 0 reserved [7] r/w reserved 1 0 reserved [8] r/w reserved 1 0 reserved [9] r/w reserved 1 0 reserved 1.4 reg 02h refdiv register (default 000001h) bit type name width default description [13:0] r/w rdiv 14 1 reference divider r value divider use also requires refbufen reg08[3]=1and divider min 1d max 16383d 1.5 reg 03h frequency register - integer part (default 000019h) bit type name width default description [18:0] r/w intg 19 25d vco divider integer part, used in all modes ) fractional mode min 20d max 2 19 -4 = 7fffch = 524,284d integer mode min 16d max 2 19 -1 = 7ffffh = 524,287d 1.6 reg 04h frequency register - fractional part (default 000000h) bit type name width default description [23:0] r/w frac 24 0 vco divider fractional part (24-bit unsigned) see fractional frequency tuning used in fractional mode only (n frac = reg 04h /2 24 min 0d max 2 24 -1 information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 22 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz 1.7 reg 05h vco spi register (default 000000h) bit type name width default description [2:0] r/w vco subsystem_id, 3 0 internal vco subsystem id [6:3] r/w vco subsystem register address 4 0 for interfacing with the vco please see section 1.3.1 . [15:7] r/w vco subsystem data 9 0 data note: reg 05h is a special register used for indirect addressing of the vco subsyst em. writes to reg 05h are automatically forwarded to the vco subsystem by the vco spi state machine cont roller. reg05h is a read-write register. however, reg05h only holds the conte nts of the last transfer to the vco subsystem. hence it is not possible to read the full contents of the vco subsystem. only the con tent of the last transfer to the vco subsystem can be read. please take note special considerations for au tocal related to reg 05h 1.8 reg 06h sd cfg register (default 200b4ah) bit type name width default description [1:0] r/w seed 2 2 selects the seed in fractional mode 00: 0 seed 01: lsb seed 02: b29d08h seed 03: 50f1cdh seed note; writes to this register are stored in the HMC1035LP6GE and are only loaded into the modulator when a frequency change is executed and if autoseed reg06h[8] =1 [3:2] r/w reserved 2 2 reserved [6:4] r/w reserved 3 4 reserved [7] r/w frac_bypass 1 0 0: use modulator, required for fractional mode, 1: bypass modulator, required for integer mode note: in bypass fractional modulator output is ignored, but fractional modulator continues to be clocked if frac_ rstb =1, can be used to test the isolation of the digital fractional modulator from the vco output in integer mode [8] r/w reserved 1 1 reserved [9] r/w reserved 1 1 reserved [10] r/w reserved 1 0 program 1 [11] r/w sd enable 1 1 0: disable frac core, use for integer mode or integer mode with csp 1: enable frac core, required for fractional mode, or integer isolation testing this register controls whether autocal starts on an integer or a fractional write [12] r/w reserved 1 0 reserved [13] r/w reserved 1 0 reserved [15:14] r/w reserved 2 0 reserved [17:16] r/w reserved 2 0 reserved [18] r/w reserved 1 0 reserved [20:19] r/w reserved 2 0 reserved [21] r/w reserved 1 1 program 0 [22] r/w reserved 1 0 reserved information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 23 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz 1.9 lock detect: HMC1035LP6GE features a robust digital lock detect function that provides faster and more accurate lock detect information compared to conventional analog lock detect schemes, and offers serial port monitoring of lock detect for visibility into device status from the host controller. lock detect enable reg 07h[3]=1 is a global enable for all lock detect functions. the lock detect circuit effectively measures the difference between the arrival of the reference and the divided vco signals at the phase detector. the arrival time difference must consistently be less than the lock detect window length, to declare lock. either signal may arrive irst, only the difference in arrival times is considered. wincnt_max in reg 07h[2:0] deines the number of consecutive counts of the divided vco that must land inside the lock detect window to declare lock. 1.9.1 analog or digital lock detect analog lock detect the lock detect window may be generated by either an analog one shot circuit or a digital one shot based upon an in- ternal timer. clearing reg 07h [6]=0 will result in a ixed, analog, nominal 10 ns window, as shown in figure 28 below. the analog window cannot be used if the pd rate is above 50 mhz, or if the charge pump offset is too large. if charge pump offset or pd frequency are changed signiicantly then the lock detect window may need to be adjusted. figure 28. lock detect 1.9.2 digital lock detect: setting reg 07h [6]=1 will result in a variable length lock detect window based upon an internal digital timer. the timer period is set by the number of cycles of the internal ld clock as programmed by reg 07h[9:7]. the ld clock frequen- cy is adjustable by reg 07h[11:10]. the ld clock signal (ring osc) can be viewed via the gpo test pins. optimal spectral performance in fractional mode requires cp current an d cp offset current coniguration discussed in detail in section 1.11 charge pump current selection . these settings in reg 09h impact the required ld window size in fractional mode of operation. to function, the required lock detect w indow size is provided by (eq 1) . information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 24 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz ( ) ( ) ( ) ( ) ( ) ( ) ( ) 9 1 2.66 10 sec ld window seconds in fractional mode 2 1 ld window seconds in integer mode 2 cp offset pd cp pd pd ia f hz i a f hz f ? ?? ?? + + ?? ?? == where: f pd : is the comparison frequency of the phase detector i cp offset : is the charge pump offset current reg 09h [20:14] i cp : is the full scale current setting of the switching charge pump reg 09h [6:0], or reg 09h [13:7] (eq 1) if the result provided by (eq 1) is equal to 10 ns analog ld can be used ( reg 07h [6] = 0). otherwise digital ld is necessary reg 07h [6] = 1. table 17 provides the required reg 07h settings to appropriately program the digital ld window size. from table 17 , simply select the closest value in the digital ld window size columns to th e one calculated in (eq 1) and program reg 07h [11:10] and reg 07h [9:7] accordingly. table 17. typical digital lock detect window ld timer speed reg07[11:10] digital lock detect window size nominal value (ns) fastest 00 6.5 8 11 17 29 53 100 195 01 7 8.9 12.8 21 36 68 130 255 10 7.1 9.2 13.3 22 38 72 138 272 slowest 11 7.6 10.2 15.4 26 47 88 172 338 ld timer divide setting reg07[9:7] 000 001 010 011 100 101 110 111 1.9.2.1 digital window coniguration example assuming, fractional mode, with a 50 mhz pd and ? charge pump gain of 2 ma ( reg 09h [13:7] = 64h, reg 09h [6:0] = 64h), ? up offset ( reg 09h [22:21] = 01b) ? and offset current magnitude of +400 a ( reg 09h [20:14] = 50h) applying (eq 1) , the required ld window size is: ( ) ( ) ( ) ( ) ( ) ( ) 3 9 63 6 0.4 10 1 2.66 10 sec 50 10 2 10 50 10 ld window seconds 13.33 nsec 2 xa hz x a hz ? ? ? ???? + + ?? ?? = = (eq 2) locating the table 17 value that is closest to the (eq 2) result, in this case 13.3 13.33. to set the digital ld window size, simply program reg 07h [11:10] = 10b and reg 07h [9:7] = 010b according to table 17 . there is always a good solution for the lock detect window for a g iven operating point. the user should understand however that one solution does not it all operating points. as observed fro m (eq 1) , if charge pump offset or pd frequency are changed signiicantly then the lock detect window may need to be a djusted. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 25 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz 1.9.3 declaration of lock: the lock detect flag status is always readable in reg 12h [1], if locked = 1. lock detect status is also output to the ld_sdo pin according to reg 0fh[4:0]=1. again, if locked, ld_sdo will be high. clearing reg 0fh [6]=0 will display the lock detect flag on ld_sdo except when a serial port read is requested, in which case the pin reverts temporar- ily to the serial data out pin, and returns to the lock detect flag after the read is completed. 1.9.4 reg 07h lock detect register (default 00014dh) bit type name width default description [2:0] r/w lkd_wincnt_max 3 5d lock detect window sets the number of consecutive counts of divided vco that must land inside the lock detect window to declare lock 0: 5 1: 32 2: 96 3: 256 4: 512 5: 2048 6: 8192 7: 65535 [3] r/w enable internal lock detect 1 1 1: enabled [5:4] r/w reserved 2 0 reserved [6] r/w lock detect window type 1 1 lock detection window timer selection 1: digital programmable timer 0: analog one shot, nominal 10 ns window [9:7] r/w ld digital window duration 3 2 0 lock detection - digital window duration 0: 1/2 cycle 1: 1 cycle 2: 2 cycles 3: 4 cycles 4: 8 cycles 5: 16 cycles 6: 32 cycles 7: 64 cycles [11:10] r/w ld digital timer frequency control 2 0 lock detect digital timer frequency control 00 fastest, 11 slowest [12] r/w reserved 1 0 reserved [13] r/w reserved 1 0 reserved information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 26 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz 1.10 reg 08h analog en register (default c1beffh) bit type name width default description [0] r/w reserved 1 1 reserved [1] r/w reserved 1 1 reserved [2] r/w reserved 1 1 reserved [3] r/w reserved 1 1 reserved [4] r/w reserved 1 1 reserved [5] r/w gpo_pad_en 1 1 0 - pin ld_sdo disabled 1 - and regfh[7]=1 , pin ld_sdo is always on required for use of gpo port 1 - and regfh[7]=0 spi ldo_spi is off if unmatched chip address is seen on the spi, allowing a shared spi with other compatible parts [6] r/w reserved 1 1 reserved [7] r/w reserved 1 1 reserved [8] r/w reserved 1 0 reserved [9] r/w prescaler clock enable 1 1 reserved [10] r/w vco buffer and prescaler bias enable 1 1 vco buffer and prescaler bias enable [11] r/w reserved 1 1 reserved [14:12] r/w reserved 3 011 reserved [17:15] r/w reserved 3 011 reserved [18] r/w reserved 1 0 reserved [19] r/w reserved 1 0 reserved [20] r/w reserved 1 0 reserved [21] r/w high frequency reference 1 0 program to 1 for xtal > 200 mhz [22] r/w reserved 1 1 reserved [23] r/w reserved 1 1 reserved 1.11 charge pump current selection HMC1035LP6GE features provides a charge pump current with programma ble gain. this enables the user to reine and maintain optimal pll loop bandwidth over a wide range of output frequenc ies and feedback divide ratios. a straight forward method for determining the charge pump gain setting fo r a ixed loop ilter (e.g., 127 khz) and reference frequency (e.g., 50mhz) is to follow the following equation: icp_up = icp_dn = 1.1ma + (2.3ma C 1.1ma) * (fvco C 1.5 ghz) / (3 ghz C 1.5 ghz) here, charge pump current (icp) is linearly modiied to compensate for the fe edback divide ratio (n) as it scales with vco output frequency (fvco). the charge pump current is set by register coniguration (reg_09h [6:0] an d reg_09h [13:7]). charge pump phase offset C fractional mode the HMC1035LP6GE provides a programmable charge pump phase offset fea ture to aid in minimizing integer boundary spurs and maintain low in-band phase noise, while the pll is in frac tional mode of operation. phase offset is achieved by introducing a constant leakage current in to the loop ilter. the amount of leak- information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 27 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz age current that is recommended is related to the charge pump gain (icp) and the p fd comparison frequency (fcomp) by the following equation(s): tcomp = 1 / fcomp i_leak = (2.5x10-9 + 4*tvco) * icp / tcomp where: tvco: is the rf period at the input of the feedback divider icp: is the selected charge pump current leakage (i_leak) can be applied with either positive or negative curren t driven into the loop ilter, (up or down respectively). up leakage is recommended for the HMC1035LP6GE. leakage magnitude and direction are set through registers reg_09h [2 0:14] and reg_09h [22], respectively. 1.12 reg 09h charge pump register (default 403264h) bit type name width default description [6:0] r/w cp dn gain 7 100d 64h charge pump dn gain control 20 astep affects fractional phase noise and lock detect settings 0d = 0 a 1d = 20 a 2d = 40 a ... 127d = 2.54ma [13:7] r/w cp up gain 7 100d 64h charge pump up gain control 20 a per step affects fractional phase noise and lock detect settings 0d = 0 a 1d = 20 a 2d = 40 a ... 127d = 2.54ma [20:14] r/w offset magnitude 7 0 charge pump offset control 5 a/step affects fractional phase noise and lock detect settings 0d = 0 a 1d = 5 a 2d = 10 a ... 127d = 635 a [21] r/w offset up enable 1 0 recommended setting = 1 in fractional mode, 0 otherwis e [22] r/w offset dn enable 1 1 recommended setting = 0 [23] r/w reserved 1 0 reserved information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 28 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz 1.13 reg 0ah vco autocal coniguration register (default 002205h) bit type name width default description [2:0] r/w vtune resolution 3 5 r divider cycles 0 - 1 1 - 2 2 - 4 3 - 8 4 - 32 5 - 64 6 - 128 program this value 7 - 256 [5:3] r/w reserved 3 0 reserved [7:6] r/w reserved 2 0 program 01 [9:8] r/w reserved 2 0 reserved [10] r/w force curve 1 0 program 0 [11] r/w bypass vco tuning 1 0 program 0 for normal operation using vco auto calibration [12] r/w no vspi trigger 1 0 program 0 for normal operation. if 1, serial transfers to vco sub-system (via reg 05h ) are disabled [14:13] r/w fsm/vspi clock select 2 1 set the autocal fsm and vspi clock (50 mhz maximum) 0: input crystal reference 1: input crystal reference/4 2: input crystal reference/16 3: input crystal reference/32 [15] r/w reserved 1 0 program 0 for normal operation. program 1 only for bist use [16] r/w reserved 1 0 reserved information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 29 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz 1.14 reg 0bh pd register (default 0f8061h) bit type name width default description [2:0] r/w pd_del_sel 3 1 sets pd reset path delay (recommended setting 001) [3] r/w reserved 1 0 reserved [4] r/w reserved 1 0 reserved [5] r/w pd_up_en 1 1 enables the pd up output [6] r/w pd_dn_en 1 1 enables the pd dn output [8:7] r/w csp mode 2 0 cycle slip prevention mode extra current is driven into the loop ilter when the phase error is larger than: 0: disabled 1: 5.4ns 2: 14.4ns 3: 24.1ns this delay varies by +- 10% with temperature, and +- 12% with process. [9] r/w force cp up 1 0 forces cp up output on - use for test only [10] r/w force cp dn 1 0 forces cp dn output on - use for test only [11] r/w reservedl 1 0 reserved [14:12] r/w reserved 3 0 reserved [16:15] r/w reserved 2 3 reserved [18:17] r/w reserved 2 3 reserved [19] r/w reserved 1 1 reserved [21:20] r/w reserved 2 0 reserved [23:22] r/w reserved 2 0 reserved 1.15 exact frequency mode hittites family of clock generation products have a unique feature cal led exact frequency mode which allows nearly arbitrary frequency conversion, or gear ratios. there are 5 registers which control the 3 frequency dividers in the part, and th us the overall frequency translation ratio: 1) reference divider (r) C pll register 2 - takes in up to 350mhz reference, and op tionally divides down to < 100mhz for the pfd comparison rate. 2) vco n-divider (ndiv) C integer (pll reg 3) + fractional section (pll reg 4). accepts values from 16 to 525287 in integer mode, or 20.0 to 242284.0 in fractional mode 3) vco output divider (nout) C vco register 2. the output frequency is given by: gear ratio = (1/r) * (ndiv) * (1/nout) since the pll supports a fractional division ratio, n can be further broken down into a fraction n = (m/n). to achieve a certain multiplication ratio, we recommend the following procedure C along with a worked example. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 30 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz example: assume we want a multiplication ratio of m/n = 944/255, with an input frequency of 168.04mhzthus fout ~ 622mhz. 1) calculate nout: determine the fundamental frequency of the vco, relat ive to your desired output frequency. the vco cores run internally from 1.5 to 3ghz. a. since the vco output divider is only capable of even division ratios, ther e is a factor of 2 in the calculation. b. nout = 2*loor(fmax/(2*fout)) eg. nout = 2 * loor ( 3g / 2*622m ) nout=2 * loor (2.41 ) nout = 2 * 2 nout = 4 so the vco will run at ~ 4 * 622 mhz. 2) calculate rdiv: determine if the rdivider needs to be used to keep the pfd rate u nder its limit, and if so, its value. a. the pfd comparison rate can be as high as 100mhz. to avoid a 2 stage locking proc ess, we rec- ommend running the pfd below 70mhz. b. r = ceiling ( fpfd_max / freference ) eg. r = ceiling ( 168.04mhz / 70 mhz) r = ceiling ( 2.4 ) r = 3 so the pfd comparison rate will be 168.04mhz / 3, or ~ 56mhz 3) calculate ndiv: we have now determined an r and nout value which keep the p ll in a valid operating condi- tion, and we are left to choose the fractional division ratio ndiv which provide s the desired gear ratio. a. calculate the desired ndiv value (which could be a fraction) , such that you r overall gear ratio is maintained: i. (m / n)_desired = (1/r) * ndiv * (1/nout) ii. ndiv = (m / n)_desired * r * nout eg. ndiv = (944 / 255 ) * 3 * 4 ndiv = 11328 / 255 b. reduce the fraction into a integer + fractional portion: eg. ndiv = 11328 / 255 ndiv = 44 + 108/255 = nint + (num / den) ndiv = ~ 44 + 0.423 c. conirm that the minimum divide ratio limit is respected. in fractional mo de, the minimum divide ratio is 20.0, in integer mode it is 16. if ndiv is too low, increase the reference divide r atio (step 2b), and recalculate. for example, doubling the reference divide ratio r, wil l double the corresponding ndiv setting. eg. in this example, ndiv of ~ 44.4 is > 20.0, so it is accetptable and r of 3 is okay. 4) calculate the integer, and approximate fractional setpoint to imple ment ndiv calculated in step 3. example nint = loor (ndiv) nint = 44 nfrac = ceil(2^24 * (ndiv-nint)) nfrac = ceiling(16,777216 * 108/255) = ceiling(7,105,644.424) = 7,10 5,644 dec 5) note that the 24-bit quantized ndiv ratio = 44 + (7,105,644 / 16,777,216) h as a slight frequency offset of ~2.3hz relative to the desired ratio of 44 + 108/255. to eliminate this offset, and gen erate the exact multiplication ratio the user desires, set the exact frequency counter (reg0ch) to the reduced denom inator as calculated in step 3b. exact frequency counter = den (from step 3b) eg. set register 0ch = 255 dec. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 31 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz 1.15.1 reg 0ch exact frequency mode register (default 000000h ) bit type name width default description [13:0] r/w number of channels per fpd 14 0 comparison frequency divided by the correction rate, must be an integer. frequencies at exactly the correction rate will have zero frequency error. 0: disabled 1: disabled 2:16383d (3fffh) 1.16 gpo_ld/sdo register HMC1035LP6GE features a gpo (general purpose output) that enables us ers to control and read various states of the device including pll and vco properties. the HMC1035LP6GE shares the ld_sdo (lock-detect/serial data out ) pin to perform various functions. it is driv- en by a tri-state cmos driver with ~200 rout. in its default coniguration, afte r power-on-reset, the output driver is disabled, and only drives during appropriately addressed spi read s. this allows it to share the output with other devices on the same bus. to monitor any of the gpo signals, including lock dete ct, set reg 0fh [7] = 1 to keep the sdo driver always on. this stops the ldo driver from tristating and means that t he sdo line cannot be shared with other devices. the signals available on the gpo are selected by changing gpo select, reg 0fh [4:0]. 1.16.1 reg 0fh gpo_ld/sdo register (default 000001h) bit type name width default description [4:0] r/w gpo_select 5 1d signal selected here is output to sdo pin when enabled 0: data from reg0f[5] 1: lock detect output 2. lock detect trigger 3: lock detect window output 4: ring osc test 5. pullup hard from csp 6. pulldn hard from csp 7. reserved 8: reference buffer output 9: ref divider output 10: vco divider output 11. modulator clock from vco divider 12. auxiliary clock 13. aux spi clock 14. aux spi enable 15. aux spi data out 16. pd dn 17. pd up 18. sd3 clock delay 19. sd3 core clock 20. autostrobe integer write 21. autostrobe frac write 22. autostrobe aux spi 23. spi latch enable 24. vco divider sync reset 25. seed load strobe 26.-29 not used 30. spi output buffer en 31. soft rstb [5] r/w gpo test data 1 0 1 - gpo test data information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 32 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz 1.16.1 reg 0fh gpo_ld/sdo register (default 000001h) bit type name width default description [6] r/w prevent automux sdo 1 0 1- outputs gpo data only 0 - automuxes between sdo and gpo data [7] r/w ldo driver always on 1 0 1- ld_sdo pin driver always on 0 - ld_sdo pin driver only on during spi read cycle [8] r/w disable pfet 1 0 program to 0 [9] r/w disable nfet 1 0 program to 0 1.17 reg 10h vco tune register (default 000020h) bit type name width default description [7:0] ro vco switch setting 8 32 read only register. indicates the vco switch setting selected by the autocal state machine to yield the nearest free running vco frequency to the desired operating frequency. not valid when reg10h[8] = 1, autocal busy. note if a manual change is done to the vco switch settings this register will not indicate the current vco switch position. 0 = highest frequency 1 = 2nd highest ... 255 = lowest frequency note: vco subsystems may not use all the msbs, in which case the unused bits are dont care [8] ro autocal busy 1 0 busy when autocal state machine is searching for the nearest switch setting to the requested frequency. 1.18 reg 11h sar register (default 007fffh) bit type name width default description [18:0] ro sar error mag counts 19 2 19 -1 sar error magnitude counts [19] ro sar error sign 1 0 sar error sign 0=+ve 1=-ve 1.19 reg 12h gpo2 register (default 000000h) bit type name width default description [0] ro gpo 1 0 gpo state [1] ro lock detect 1 0 lock detect status 1 = locked 0 = unlocked 1.20 reg 13h bist register (default 000000h) bit type name width default description [15:0] ro reserved 19 4697d reserved [16] ro reserved 1 0 reserved information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 33 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz 2.0 vco subsystem register map please note that the vco subsystem uses indirect addressing vi a reg 05h . for more detailed information on how to write to the vco subsystem please see section 1.3 vco serial port interface (spi) . 2.1 vco_reg 00h tuning bit type name width default description [0] wo cal 1 0 vco tune voltage is redirected to a temperature compensated calibration voltage [8:1] wo caps 8 16 vco sub-band selection. 0 - max frequency 1111 1111 - min fre quen cy. not all sub-bands are used on the various products. 2.2 vco_reg 01h enables bit type name width default description [0] wo master enable vco subsystem 1 1 0 - all vco subsystem blocks off [1] wo vco enable 1 1 enables vcos [2] wo pll buffer enable 1 1 enables pll buffer to n divider [3] wo io master enable 1 1 enables output stage and the output divider. it does not enable/disable the vco. [4] wo spare 1 1 dont care [5] wo output stage enable 1 1 output stage enable [7:6] wo reserved 2 11 reserved [8] wo dont care 1 1 dont care for example, to disable the output stage of the vco subsystem of the hmc1035lp6 ge, bit 5 in vco_reg 01h needs to be cleared. if the other bits are left unchanged, then 1 1101 1111 need s to be written into vco_reg 01h . the vco subsystem register is accessed via a write to pll subsystem reg 05h = 1 1101 1111 0001 000 = ef88h reg 05h [2:0] = 000; vco subsystem id 0 reg 05h [6:3] = 0001; vco subsystem register address reg 05h [7] = 1; master enable reg 05h [8] = 1; vco enable reg 05h [9] = 1; pll buffer enable reg 05h [10] = 1; io master enable reg 05h [11] = 1; reserved reg 05h [12] = 0; disable the output stage reg 05h [14:13] = 01b reg 05h [15] = 1; dont care 2.3 vco_reg 02h biases bit type name width default description [5:0] wo rf divide ratio 6 1 0 - mute 1 - fo 2 - fo/2 3 - invalid, defaults to 2 4 - fo/4 5 - invalid, defaults to 4 6 - fo/6 ... 60 - fo/60 61 - invalid, defaults to 60 62 - fo/62 > 62 - invalid, defaults to 62 [7:6] wo reserved 2 0 reserved [8] wo dont care 1 0 dont care information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 34 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz for example, to write 0_0011_1110 into vco_reg 03h vco subsystem (vco_id = 000b), and set the vco output divider to divide by 62, the following needs to be written to reg 05h =0_0011_1110, 0010, 000 b. reg 05h [2:0] = 00; subsystem id 0 reg 05h [6:3] = 0010; vco register address 2d reg 05h[ 16:7] = 0_0011_1110; divide by 62 HMC1035LP6GE power versus performance priority modes: the HMC1035LP6GE is designed with 2 major coniguration options: power p riority and performance priority. the power priority setting reduces the current consumption of the part, whe reas the performance priority setting improves the jitter and phase noise performance. the settings are selected via the a ppropriate spi registers, vco_reg 03h [1:0]. the power priority mode is used in order to reduce the curren t consumption from 237 ma to 173 ma, such as may be required in power sensitive applications, where the lowest phase noi se performance may not be critical. the power priority mode does not cause a reduction on the output signal power, but it deg rades the phase noise, and thus jitter, performance. in order to realize the best phase noise and jitter performanc e, the HMC1035LP6GE should be operated in the performance priority mode. by invoking this mode, the phase noise wil l improve or decrease by 10 db resulting in a -163 dbc/hz loor. the performance priority mode is optimal in driving t he sample clock inputs of adc/dacs and high speed serdes reference clock inputs where jitter performance is of u tmost importance. the power versus performance priority mode is set by the vco_reg03h bits [1 :0] and the default condition is power priority mode, bit set to a logic 1. 2.4 vco_reg 03h conig bit type name width default description [1:0] wo power- performance priroirty 2 2 selects output noise loor performance level at a cost of increased current consumption 01: power priority lowest current consumption 11: performance priority best phase noise other states (00 and 10) not supported. [2] wo rf_p output enable 1 0 logic 1 enables the output on rf_p pin. required for differential operation, or single-ended output on rf_p pin. [3] wo rf_n output enable 1 0 logic 1 enables the output on rf_n pin. required for differential operation, or single-ended output on rf_n pin. [4] wo internal termination enable 1 1 logic 1 enables the internal bias termination, is used for lvds level outputs. set to logic 0 for external termination [5] wo increase internal output resistance 1 0 logic 1 increases internal output termination by ~ 15 on each pin (rf_n and rf_p) [6] wo reserved 1 0 reserved [8:7] wo mute mode 2 1 deines when the mute function is enabled (the output is muted): ? 00: mute enabled when divide ratio ( vco_reg 02h [5:0] = 0 ? 01: during vco calibration ( ? 10: during vco calibration or when lock detect/ gpo output is off (for more information see section gpo_ld/sdo register ? 11: mute always on. information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 35 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz 2.5 vco_reg 04h cal/bias speciied performance is only guaranteed with the required settings i n this table. other settings are not supported. bit type name width default description [0] wo reserved 1 1 reserved [1] wo reserved 1 0 reserved [2] wo reserved 1 0 reserved [4:3] wo reserved 2 1 reserved [6:5] wo reserved 2 2 reserved [8:7] wo reserved 2 1 reserved 2.6 vco_reg05h cf_cal bit type name width default description [1:0] wo reserved 2 2 reserved [3:2] wo reserved 2 2 reserved [5:4] wo reserved 2 2 reserved [7:6] wo reserved 2 2 reserved [8] wo reserved 1 0 reserved 2.7 vco_reg06h msb cal bit type name width default description [1:0] wo reserved 2 3 reserved [3:2] wo reserved 2 3 reserved [5:4] wo reserved 2 3 reserved [7:6] wo reserved 2 3 reserved [8] wo reserved 1 0 reserved 2.8 vco_reg 07h msb cal bit type name width default description [3:0] wo output stage gain control 4 0001 0000 -> output = 690 mv 0001 -> output = 780 mv 0010 -> output = 900 mv 0011 -> output = 980 mv 0100 -> output = 1100 mv 0101 -> output = 1260 mv 0110 -> output = 1400 mv 0111 -> output = 1590 mv 1000 -> output = 1810 mv 1001 -> output = 1980 mv 1010 -> output = 2250 mv 1011 -> output = 2560 mv 1100 -> invalid 1110 -> invali d 1111 -> invali d [4] wo reserved 1 1 reserved [6:5] wo reserved 2 3 program 00 [7] wo reserved 1 1 reserved [8] wo reserved 1 0 reserved note: all reserved bits should be programmed to default conditions unless noted otherwise in the description column information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 36 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz HMC1035LP6GE application information the HMC1035LP6GE features a lexible output frequency range (25 mhz to 250 0 mhz), industry leading phase noise and phase jitter performance, excellent noise loor (<-162 dbc/hz), an d a high level of integration. HMC1035LP6GE is ideal as a high frequency, low jitter processor clock, a clock source for hig h-frequency data converters or as a reference oscillator for physical layer devices (phy). the HMC1035LP6GE can also be used as an lo for 10g/40g/100g optical mod ules and transponders, as a reference clock for 10g/40g/100g line cards, and for jitter attenuation and freque ncy translation. synchronous ethernet, sonet/ sdh, and otn applications often require jitter attenuation and frequ ency translation on the recovered line clock. figure 29. HMC1035LP6GE in a typical transmit chain information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 37 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz HMC1035LP6GE application information the HMC1035LP6GE can also be used as an lo for 10g optical modules and transponders ( figure 30 ), as a reference clock for 1g/10g line cards (figure 31), and for jitter attenuation and frequency translation ( figure 32 ) . synchronous ethernet, sonet/sdh, and otn applications often require jitter attenuation and frequency translation on the recovered line clock. figure 30. HMC1035LP6GE used as a local oscillator (lo) for 10g modules/transponders figure 31. HMC1035LP6GE used as a reference clock for 1g/10g line cards information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 38 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz HMC1035LP6GE application information figure 32. HMC1035LP6GE used in a jitter attenuation application for synchronous e thernet & line timing information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d
for price, delivery and to place orders: hittite microwave corporation, 2 e lizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite .com application support: phone: 978-250-3343 or apps@hittite.com clock generators - smt 39 HMC1035LP6GE v02.0614 high performance, +3.3 v clock generator 25 - 2500 mhz line and reference clock rate otn line rates (gbps) typical reference clock rates (mhz) otu2 10.709 669.31 167. 3 3 otu2e 11.0 9 5 693.44 173.36 otu1e 11.0 49 690.56 172.64 otu2f 11.317 707.31 176.83 otu1f 11. 27 704.38 176.09 otu3 43.018 2688.63 672.16 otu4 111.8 0 9 1747.0 2 otu4v 127.15 6 1986.82 sonet/sdh sts-192/stm-64 9.95328 622.08 155.52 sts-768/stm-256 39.81312 2488.32 622.08 ethernet 10ge lan 10.3125 156.25 10ge wan 9.95328 622.08 155.52 xaui (4 x 3.125g) 3.125 156.25 40ge (4 x 10g) 10.3125 156.25 100ge (4 x 25g) 25.78125 805.66 156.25 fibre channel (fc) 10gfc 10.52 164.38 16gfc 14.025 212.5 32gfc 28.5 425 information furn is hed by an al og devices is believed to be a cc urate and re lia bl e. however, no responsibility is assumed by an al og devices for its u se , no r for any infring em en ts of pat en ts or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. for price, delivery, and to place o rd ers: an al og devices, inc., one techn ol ogy way, p.o. box 9106, norwood, ma 02062-9106 phone: 781-329-4700 o rd er online at ww w.an al og .com app li cation sup po rt: p ho ne: 1-800-analog-d

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